Silicon pillar thickness effect on vertical double gate MOSFET (VDGM) with oblique rotating implantation (ORI) method

Ismail Saad, and Munawar Agus Riyadi, and Razali Ismail, (2008) Silicon pillar thickness effect on vertical double gate MOSFET (VDGM) with oblique rotating implantation (ORI) method. In: 2008 IEEE International Conference on Semiconductor Electronics (ICSE 2008), 25-27 November 2008, Johor, Malaysia.

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Official URL: http://dx.doi.org/10.1109/SMELEC.2008.4770367

Abstract

The silicon pillar thickness effect on vertical double gate MOSFET (VDGM) fabricated by implementing oblique rotating ion implantation (ORI) method is investigated. For this purpose, several silicon pillar thicknesses tsi were simulated. The source region was found to merge at tsi < 57 nm, forming floating body effect. The electron-hole concentration along the channel and the depletion isolation region shows different shape and broaden in smaller tsi. For several channel lengths Lg ≤ 100nm, in the reduction of pillar thickness, the sub-threshold slope (SS) tends to decrease, which indicate an increase in gate-gate charge coupling. Other short channel effect parameters (Ioff, IDsat) show better improvement for lower pillar thickness, thus offer better performance and control. © 2008 IEEE.

Item Type:Conference Paper (UNSPECIFIED)
Uncontrolled Keywords:Channel length, Electron hole, Floating body effect, Gate charges, Short-channel effect, Silicon pillar, Source region, Subthreshold, Thickness effect, Vertical double gate
Subjects:?? TK7800-8360 ??
Divisions:SCHOOL > School of Engineering and Information Technology
ID Code:1618
Deposited By:IR Admin
Deposited On:25 Mar 2011 10:38
Last Modified:30 Dec 2014 15:00

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