Investigation of short channel immunity of fully depleted double gate MOS with vertical structure

Riyadi, Munawar A. and Suseno, Jatmiko E. and Napiah, Zul Atfyi F.M. and Afifah Maheran A. Hamid and Ismail Saad and Razali Ismail (2010) Investigation of short channel immunity of fully depleted double gate MOS with vertical structure. In: 2010 IEEE International Conference on Semiconductor Electronics (ICSE 2010), 28-30 June 2010, Melaka, Malaysia.

Full text not available from this repository.


The electrical performance of fully depleted double gate MOSFET devices with vertical structure feature were evaluated with the implementation of oblique rotating implantation (ORI) method for several silicon pillar thicknesses using virtual wafer tool. The difference in the subthreshold performance is well noticed, as well as the potentials across the channel for different geometries. The implication of channel length reduction shows that in fully depleted feature, thinner pillar will result in better subthreshold performances than the thicker structure while maintaining the high on-current. As a result, thinner pillar delivers better short channel characteristic control in further channel scaling up to 20 nm. © 2010 IEEE.

Item Type: Conference or Workshop Item (UNSPECIFIED)
Uncontrolled Keywords: Channel length, Different geometry, Double gate, Double-gate mosfet devices, Electrical performance, Fully depleted, On-currents, Scaling-up, Short channels, Silicon pillar, Subthreshold, Vertical structures, MOSFET devices, Silicon wafers, Semiconducting silicon compounds
Subjects: ?? TK7800-8360 ??
Divisions: SCHOOL > School of Engineering and Information Technology
Depositing User: ADMIN ADMIN
Date Deposited: 28 Feb 2011 07:07
Last Modified: 30 Dec 2014 01:27

Actions (login required)

View Item View Item