Numerical simulation analysis of CMOS compatible process of 50 nm vertical single and double gate NMOSFET

Ismail Saad, and Razali Ismail, (2010) Numerical simulation analysis of CMOS compatible process of 50 nm vertical single and double gate NMOSFET. In: International Conference on Advancement of Materials and Nanotechnology (ICAMN 2007), 29 May - 1 June 2007, Kedah, Malaysia.

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Abstract

Vertical MOSFET's have been proposed in the roadmap of semiconductor as a candidate for sub-100 nm CMOS technologies. In this paper, unique architecture of single and double gate vertical NMOS transistor is proposed that retained its CMOS compatibility. The MOSFET was fabricated by using oblique rotating ion implantation (ORI) technique addressed by numerical simulation. An electrical characterization of the device demonstrated a suppression of short channel effects (SCE) that was quantitatively given by an analysis of transfer and output characteristics with a reasonable value of threshold voltage (V T), drive and off -leakage current (ION and I OFF), saturation current (IDSat), subthreshold swing (S) and Drain Induced Barrier Lowering (DIBL). These results show that the vertical transistor is seen to offer considerable advantages down to the 100 nm node and beyond due to the dual or surround channels and the ability to produce a 50 nm channel length with relax lithography. © 2010 American Institute of Physics.

Item Type: Conference or Workshop Item (UNSPECIFIED)
Uncontrolled Keywords: CMOS, DIBL, Double gate MOSFET, Vertical MOSFET
Subjects: ?? TK7885-7895 ??
Divisions: SCHOOL > School of Engineering and Information Technology
Depositing User: Unnamed user with email storage.bpmlib@ums.edu.my
Date Deposited: 07 Mar 2011 08:07
Last Modified: 29 Dec 2014 08:15
URI: http://eprints.ums.edu.my/id/eprint/2067

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