Numerical analysis of vertical double gate MOSFETs (VDGM) with dielectric pocket (DP) effects on silicon pillar for nanoscale transistor

Ismail Saad, and R. M. A., Lee and Munawar Agus Riyadi, and Mohammad Taghi Ahmadi, and Razali Ismail, (2009) Numerical analysis of vertical double gate MOSFETs (VDGM) with dielectric pocket (DP) effects on silicon pillar for nanoscale transistor. In: International Conference on Nanoscience and Nanotechnology, Nano-SciTech 2008, 18-21 November 2008, Selangor, Malaysia.

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Abstract

Numerical analysis of vertical double-gate MOSFETs (VDGM) that incorporates dielectric-pocket (DP) is addressed in this paper for the suppression of short-channel effects (SCE) and bulk punch-through. The comparison between standard and VDGM-DP revealed the advantages of DP for inhibition of SCE. The transfer and output characteristics of the VDGMDP indicates a reasonable value of threshold voltage (VT), drive and off -leakage current (I ON and IOFF), sub-threshold swing (S) and Drain Induced Barrier Lowering (DIBL). The DP incorporated on top of transistor turret is revealed to increase the saturation current IDsat due to drain-end electric field reduction that improved the carrier mobility and the drain current tremendously. © 2009 American Institute of Physics.

Item Type: Conference or Workshop Item (UNSPECIFIED)
Uncontrolled Keywords: DIBL, Dielectric-pocket, Double gate, Vertical MOSFET
Subjects: ?? TK7800-8360 ??
Divisions: SCHOOL > School of Engineering and Information Technology
Depositing User: Unnamed user with email storage.bpmlib@ums.edu.my
Date Deposited: 22 Mar 2011 09:24
Last Modified: 30 Dec 2014 06:35
URI: http://eprints.ums.edu.my/id/eprint/2528

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