Performance design and simulation analysis of vertical double gate MOSFET (VDGM)

Ismail Saad, and Nurmin Bolong, and Divya, P. and Teo, Kenneth Tze Kin (2011) Performance design and simulation analysis of vertical double gate MOSFET (VDGM). In: UKSim 13th International Conference on Modelling and Simulation, UKSim 2011, 30 Macrh - 1 April 2011, Cambridge, UK..

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Design consideration of vertical MOSFET with double gate structure on each side of insulating pillar for nanodevice applications is presented. The body doping effect on vertical channel for channel length, L g = 50nm and analyzing its effect towards such small devices was successfully performed. The analysis continued with the comparative investigation of device performance with conventional planar MOSFET as scaling L g down to 50nm. The final part evaluates the innovative design of incorporating dielectric pocket (DP) on top of vertical MOSFET turret with comprehensive device performance analysis as compared to standard vertical MOSFET in nano scale realm. An optimized body doping for enhanced performance of vertical MOSFET was revealed. The vicinity of DP near the drain end is found to reduce the charge sharing effects between source and drain that gives better gate control of the depletion region for short channel effect (SCE) suppression in nanodevice structure.

Item Type: Conference or Workshop Item (UNSPECIFIED)
Uncontrolled Keywords: Dielectric Pockets, Doping effec, Planar MOSFET, Short channel effect, Vertical MOSFET, Doping effec, MOS-FET, Short channel effect, Vertical MOSFETs, Design, Nanostructured materials, Threshold voltage, MOSFET devices
Subjects: T Technology > TK Electrical engineering. Electronics Nuclear engineering
Divisions: SCHOOL > School of Engineering and Information Technology
Depositing User: Unnamed user with email
Date Deposited: 11 Oct 2012 05:57
Last Modified: 30 Dec 2014 01:39

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