Munawar Agus Riyadi and Z. A. F. M. Napiah and Ismail Saad and Razali Ismail (2008) Characterization analysis of a novel approach in fabrication of CMOS compatible vertical MOSFETs incorporating a dielectric pocket. In: 2008 IEEE International Conference on Semiconductor Electronics (ICSE 2008), 25-27 November 2008, Johor, Malaysia.
Full text not available from this repository.Abstract
The process of making novel CMOS compatible vertical MOSFET by incorporating Dielectric Pocket (DP) is shown using virtual wafer simulation tool. The corresponding device doping profiles of a junction is highlighted and demonstrated good device profiles for the feasibility of the approach. The effect of amorph Si recrystallization as the result of different RTA time is also evaluated. Both the transfer and output characteristics of the DP vertical MOSFETs indicates a reasonable value of drive and off -leakage current (I ON and IOFF), sub-threshold swing (S) and Drain Induced Barrier Lowering (DIBL). The increasing time of RTA to 100 s shows better performance of the device than for shorter time, but in the thread-off of higher drain junction depth and leakage current. ©2008 IEEE.
| Item Type: | Conference or Workshop Item (UNSPECIFIED) |
|---|---|
| Keyword: | CMOS compatible, Device profile, Doping profiles, Drain junctions, Drain-induced barrier lowering, Off-leakage current, Output characteristics, Reasonable value, Recrystallization, Simulation tool, Subthreshold swing, Vertical MOSFET, Vertical MOSFETs |
| Subjects: | T Technology > TK Electrical engineering. Electronics Nuclear engineering > TK1-9971 Electrical engineering. Electronics. Nuclear engineering > TK7800-8360 Electronics |
| Department: | SCHOOL > School of Engineering and Information Technology |
| Depositing User: | ADMIN ADMIN |
| Date Deposited: | 25 Mar 2011 12:15 |
| Last Modified: | 30 Dec 2014 14:42 |
| URI: | https://eprints.ums.edu.my/id/eprint/1614 |
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