P.Divya and Ismail Saad (2010) Feasibility study of integrated vertical and lateral IMOS and TFET devices for nano-scale transistors. In: 2010 IEEE International Conference on Semiconductor Electronics (ICSE 2010), 28-30 June 2010, Melaka, Malaysia.
Full text not available from this repository.Abstract
A review on the integration of vertical impact ionization MOSFET (IMOS) with vertical tunnelling FET (TFET) has been presented in this paper. A comparison has been done on the lateral and vertical I-MOS and TFET device structures, highlighting the advantages and drawbacks of each device. Integration of I-MOS and TFET on a vertical scale is seen as one of the promising solutions, to continue the trend of scaling down the devices further, in the nanometer regime. © 2010 IEEE.
| Item Type: | Conference or Workshop Item (UNSPECIFIED) |
|---|---|
| Keyword: | Device structures, Feasibility studies, MOS-FET, Nano-meter regimes, NanoScale Transistors, Scaling down |
| Subjects: | T Technology > TK Electrical engineering. Electronics Nuclear engineering > TK1-9971 Electrical engineering. Electronics. Nuclear engineering > TK7800-8360 Electronics |
| Department: | SCHOOL > School of Engineering and Information Technology |
| Depositing User: | ADMIN ADMIN |
| Date Deposited: | 28 Feb 2011 15:32 |
| Last Modified: | 30 Dec 2014 09:31 |
| URI: | https://eprints.ums.edu.my/id/eprint/1934 |
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