Self-aligned double-gate (DG) vertical MOSFET's using oblique rotating implantation (ORI) method with reduced parasitic capacitance

Ismail Saad, and Munawar Agus Riyadi, and Razali Ismail, and Vijay K. Arora, (2008) Self-aligned double-gate (DG) vertical MOSFET's using oblique rotating implantation (ORI) method with reduced parasitic capacitance. In: 2008 IEEE International Conference on Semiconductor Electronics (ICSE 2008), 25-27 November 2008, Johor, Malaysia.

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Abstract

Enhanced symmetrical self-aligned double-gate (DG) vertical nMOSFET with low parasitic capacitance is presented. The process utilizes the oblique rotating ion implantation (ORI) method combined with fillet local oxidation (FILOX) technology (FILOX + ORT). Self-aligned region forms a sharp vertical channel profile that increased the number of electrons in the channel. These have improved drive-on current and drain-induced-barrier-lowering (DIBL) effect with a reduced off-state leakage current tremendously. The gate-to-drain capacitance is significantly reduced while has a small difference of gate-to-source capacitance compared to FILOX device. The drain overlap capacitance is a factor of 0.2 lower and the source overlap capacitance is a factor of 1.5 lower than standard vertical MOSFETs. © 2008 IEEE.

Item Type: Conference or Workshop Item (UNSPECIFIED)
Uncontrolled Keywords: Drain overlap, Drain-induced-barrier-lowering effects, Fillet local oxidations, Gate-to-drain capacitance, Low-parasitic, NMOSFET, Number of electrons, Off-state leakage current, On currents, Overlap capacitance, Parasitic capacitance, Self aligned double gates, Self-aligned, Vertical channels, Vertical MOSFET, Vertical MOSFETs
Subjects: ?? TK7800-8360 ??
Divisions: SCHOOL > School of Engineering and Information Technology
Depositing User: Unnamed user with email storage.bpmlib@ums.edu.my
Date Deposited: 25 Mar 2011 05:11
Last Modified: 30 Dec 2014 07:00
URI: http://eprints.ums.edu.my/id/eprint/1607

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