ASIC Layout Design-Space Exploration of Pan-and-Tompkins Pre-Processing Algorithm for High Efficiency Electrocardiogram Monitor

Jia, Hui Lim and Yuan, Wen Hau and Hoe, Tung Yew and Sreedharan Baskara Dass (2020) ASIC Layout Design-Space Exploration of Pan-and-Tompkins Pre-Processing Algorithm for High Efficiency Electrocardiogram Monitor. In: 2020 IEEE 2nd International Conference on Artificial Intelligence in Engineering and Technology (IICAIET), 20 November 2020, Kota Kinabalu, Malaysia. (Submitted)

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Official URL: https://ieeexplore.ieee.org/document/9257862

Abstract

Cardiovascular diseases (CVDs) is the leading cause of the death globally. Ambulatory Electrocardiogram (ECG) and mobile monitoring is very important for early heart disease detection and prevention, but its measurement normally contains various types of noise which affect the analysis accuracy. Moreover, long hour ECG monitoring requires an efficient architecture to support real-time processing and low power consumption. This paper presents an application specific integrated circuit (ASIC) design of Pan-and-Tompkins ECG pre-processing algorithm which aims to remove several unwanted noise to increase analysis accuracy. The complete design flow covers high-level algorithm modelling in Matlab, followed by synthesizable design at Register Transfer Level (RTL) until logic synthesis, physical synthesis and static timing analysis to produce VLSI layout. Several power optimization techniques as well as different ASIC process technology libraries in terms of SilTerra’s 180nm CMOS Logic Generic Library (CL180G) and Synopsys 32nm Generic Library (SAED32) are deployed for design-space exploration to study the design trade-off in terms of power consumption, timing performance, and the logic area usage. Results show that the clock gating technique is able to reduce 32.4% of dynamic power in design using CL180G generic library, whereas the integration of several power optimization techniques using SAED32 generic library is able to reduce 43.82% of dynamic power, 91.21% of leakage power and 91.25% of total power.

Item Type:	Conference or Workshop Item (Paper)
Keyword:	Application Specific Integrated Circuit , ASIC , Electrocardiogram (ECG) preprocessing , Design-Space Exploration , low power design optimization , Pan-and-Tompkins algorithm
Subjects:	T Technology > TK Electrical engineering. Electronics Nuclear engineering > TK1-9971 Electrical engineering. Electronics. Nuclear engineering > TK7800-8360 Electronics > TK7885-7895 Computer engineering. Computer hardware
Department:	FACULTY > Faculty of Engineering
Depositing User:	NORAINI LABUK -
Date Deposited:	06 Sep 2021 13:38
Last Modified:	06 Sep 2021 13:38
URI:	https://eprints.ums.edu.my/id/eprint/30451

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