Razali Ismail and Ismail Saad (2008) Self-aligned double-gate (DG) nanoscale vertical MOSFET'S with reduced parasitic capacitance. In: Smart Structures, Devices, and Systems IV, 10-12 December 2008, Melbourne, Australia.
Full text not available from this repository.Abstract
Enhanced symmetrical self-aligned double-gate (DG) vertical nMOSFET with low parasitic capacitance is presented. The process utilizes the oblique rotating ion implantation (ORI) method combined with fillet local oxidation (FILOX) technology (FILOX + ORI). Self-aligned region forms a sharp vertical channel profile that increased the number of electrons in the channel. These have improved drive-on current and drain-induced-barrier-lowering (DIBL) effect with a reduced off-state leakage current tremendously. The gate-to-drain capacitance is significantly reduced while having a small difference of gate-to-source capacitance compared to FILOX device. The drain overlap capacitance is a factor of 0.2 lower and the source overlap capacitance is a factor of 1.5 lower than standard vertical MOSFETs. © 2008 SPIE.
| Item Type: | Conference or Workshop Item (UNSPECIFIED) |
|---|---|
| Keyword: | Double gate, Nanoscale FET, Oblique rotating ion implantation, Self-aligned, Vertical MOSFETs |
| Subjects: | T Technology > TK Electrical engineering. Electronics Nuclear engineering > TK1-9971 Electrical engineering. Electronics. Nuclear engineering > TK7800-8360 Electronics |
| Department: | SCHOOL > School of Engineering and Information Technology |
| Depositing User: | ADMIN ADMIN |
| Date Deposited: | 25 Mar 2011 12:23 |
| Last Modified: | 30 Dec 2014 15:00 |
| URI: | https://eprints.ums.edu.my/id/eprint/1613 |
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