Mohd. Zuhir Hamzah (2014) Design and analysis of vertical strained impact ionization mosfet incorporating dielectric pocket (VESIMOS-PD). Masters thesis, Universiti Malaysia Sabah.
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Abstract
CMOS device scaling faces several fundamental limits as it scaled beyond the sub- 30nm regime. Non-scalability of the subthreshold slope (S) and adverse short channel effects degrading the current drivability and electron mobility of a MOSFET. An innovative device structure with appropriate device physics understanding is vitally needed for scaling the silicon MOSFET into nanometre regime. Underlying this problem is the subthreshold slope concept, which is a measure of switching abruptness in transistor. S is fundamentally limited at 60mV/decade by the driftdiffusion based transport in current CMOS technology. Impact ionization MOSFET (IMOS) that works on the principle of avalanche breakdown mechanism has become promising candidate to overcome this S value constraint. In this thesis, the design and simulation analysis of high performance Vertical Strained SiGe IMOS incorporating Dielectric Pocket (VESIMOS-DP) towards suppressing Parasitic Bipolar Junction (PBT) effect and optimizing breakdown voltage has been successfully carried out using Sentaurus TCAD tools. With dielectric pocket (DP) of 60nm, stable threshold voltage (VTH) and excellent S value is revealed due to the reduced charge sharing effect in device active region near the DP vicinity. Furthermore, the DP layer has successfully suppressed the PBT effect for V05 2= 2.SV with higher breakdown voltage of 3.6V due to diminished electric field in the drain side intrinsic Silicon (i-Si) region. Therefore, the electron mobility was also found to be improved by 20%. Additionally, lower S value when DP is place at drain side i-Si region is shown due to significant improvement of impact ionization (II) rate. It is also revealed that with low body doping concentration, the device suffers tremendous PBT effect that prevents the device from switched off. An inverse proportional of S and VTH value was also found when S/D doping concentration increased. The effect of strain shows that the increase in Ge contents reduced VTH but increase when SiGe layer thickness (TsiGe) increases. In many aspects, it is revealed that the incorporation of DP enhanced the electrical performance and suppressed PBT effect of IMOS in nanometer regime for future development of nanoelectronic device.
| Item Type: | Thesis (Masters) |
|---|---|
| Keyword: | CMOS scaling, Subthreshold slope, Impact Ionization MOSFET, Vertical strained SiGe, Dielectric pocket |
| Subjects: | T Technology > TK Electrical engineering. Electronics Nuclear engineering > TK1-9971 Electrical engineering. Electronics. Nuclear engineering > TK7800-8360 Electronics |
| Department: | FACULTY > Faculty of Engineering |
| Depositing User: | DG MASNIAH AHMAD - |
| Date Deposited: | 16 Apr 2025 10:35 |
| Last Modified: | 16 Apr 2025 10:35 |
| URI: | https://eprints.ums.edu.my/id/eprint/43502 |
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